Category: Fpga Firmware
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dth400_p1v2_daq_15g156gty_002_005_000
Version 15 Gb It contains: Fix the read of MAC address lower part (2 bytes) from EEPROM
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dth400_p1v2_daq_25g156gty_002_005_000
Version 25 Gb It contains: Fix the read of MAC address lower part (2 bytes) from EEPROM
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dth400_p1v2_daq_15g156gty_002_004_004
Version 15 Gb It contains: Fix the bug where DAQ transfer of data stopped after a while without error. Add the FEC on DAQ link (should be enable by software to use it)
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dth400_p1v2_daq_25g156gty_002_004_004
Version 25 Gb It contains: Fix the bug where DAQ transfer of data stopped after a while without error. Add the FEC on DAQ link (should be enable by software to use it)
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dth400_p1v2_daq_25g156gty_002_004_001
Version 25 Gb It contains: Fix the bug of data corruption when huge backpressure (located in the switch stream before the ETH package)
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dth400_p1v2_daq_15g156gty_002_004_001
Version 15 Gb It contains: Fix the bug of data corruption when huge backpressure (located in the switch stream before the ETH package)
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dth400_p1v2_daq_25g156gty_002_002_002
Version 25 Gb It contains: Fix the bug of FED CRC overwritten in the Trailer
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dth400_p1v2_daq_15g156gty_002_002_002
Version 15 Gb It contains: Fix the bug of FED CRC overwritten in the Trailer
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dth400_p1v2_daq_15g156gty_002_002_001
Version 15 Gb It contains: Add the CRC value computed and the reception in a new place in the Ffragment Field Trailer Add PRBS on SR receiver and Loopback control on the sender Fixed IP line_rate values, and some timing Constraints
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dth400_p1v2_daq_25g156gty_002_002_001
Version 25 Gb It contains: Add the CRC value computed and the reception in a new place in the Ffragment Field Trailer Add PRBS on SR receiver and Loopback control on the sender Fixed IP line_rate values, and some timing Constraints